1. Field of the Invention
The present invention generally relates to a vertical transistor structure and a method of forming a contact node of the vertical transistor structure. In particular, the present invention for forming a composite contact node in the vertical transistor structure, whereby the outward contact resistance of the vertical transistor structure can be reduced.
2. Description of the Prior Art
Dynamic random access memory (DRAM) is a semiconductor element wherein a capacitor structure is electrically connected to a gate structure. The storage capacitor is the core elements of the dynamic random access memory, which is responsible for storing the signal or data. Depending on the position of the storage capacitor, the dynamic random access memory can be divided into trench type and stacked capacitor structures. When considering the manufacturing capacity, the physical limit of the material, leakage current, precision and exposure and etching processes, the stacked capacitor structure has advantage over the trench capacitor.
A trench capacitor is usually located under the gate electrode, and stacked capacitor structure is located above the gate electrode, so manufacturing steps for the stacked capacitor structure will fall after the gate electrode structure fabrication steps. Therefore, the gate structure at the time of manufacture, it will leave an upward node, to be connected with the stacked capacitor structure. Thus, when a stack capacitor structure is completed, contact node for electrically connecting the capacitor and the gate structure is formed.
However, the current process simply uses silicon as a material for the node, so the contact node does not have an ideal low contact resistance (outward contact resistance), which has become one obstacle to the performance improvement of the dynamic random access memory.